1. Field of the Invention
This invention relates to a bus control apparatus suitable for use with, for example, a computer.
2. Description of the Related Art
In a conventional computer, where a peripheral equipment such as, for example, an interface board which operates at a lower speed than the bus accessing speed of a CPU (central processing unit) of the computer is employed, if the bus accessing timing of the CPU is decreased in accordance with the bus accessing timing of the peripheral equipment, then the processing speed of the entire apparatus is reduced. Therefore, a so-called wait controller or a like apparatus is provided in order to adjust the timing at which a read signal or a write signal developed from the CPU is to be supplied to the peripheral equipment.
Further, in a conventional computer, where a peripheral equipment having a bus width different from that of the CPU is employed, in particular, where, for example, a peripheral equipment having a bus width of 8 bits is employed for a CPU that has a bus width of 32 bits, a hardware apparatus for exclusive use for packing and unpacking data is provided and data of 32 bits outputted from the CPU are divided (unpacked) into four groups of data of 8 bits to be supplied to the peripheral equipment whereas data of 8 bits outputted from the peripheral equipment are read four times to produce (pack) data of 32 bits to be supplied to the CPU.
By the way, such a wait controller as described above must be designed for each of the peripheral equipments to be connected to a computer. Accordingly, there is an issue with connectivity, but involves a high cost to resolve it.
Further, some peripheral equipments continue to output data even after the CPU has finished reading the data from the peripheral equipment, that is, have a long floating time. Further, some other peripheral equipments are required to hold data on a data bus for a while even after outputting of a data write the signal from the CPU to write data into the peripheral apparatus comes to an end, that is, have a long hold time.
For such peripheral equipments that have a long floating time or a long hold time, adjusting the operation timing of the part phrase equipment by means of a wait controller as described above is not enough, a special hardware contrivance is required.
Consquently, there is another problem to be solved that will increase the size and the cost of the apparatus.
Further, the hardware apparatus for packing and unpacking data as described above requires, similarly to a wait controller, individual designing, for example, packing-unpacking trigger generation logic in accordance with a peripheral equipment to be connected to the computer which will further increase the cost of the apparatus.
Furthermore, where a peripheral equipment having a bus width of 8 bits is employed for a CPU that has a bus width of 32 bits as described above, when four data of 8 bits obtained by unpacking a data of 32 bits outputted from the CPU are to be written into the peripheral equipment, for example, a memory, the address into which data should be written must be incremented one by one four times. But if the peripheral equipment is a FIFO (first-in first-out) for which reading and writing of data are performed at a fixed address, the peripheral equipment must be constructed so that the four data of 8 bits are written into the same fixed address.
Here in the present specification, a peripheral equipment is referred to as addressing type if its bus is different from that of a CPU and the address is incremented or fixed as described above.
The hardware apparatus described above, however, is not constructed such that the address of a peripheral equipment into or from which data are to be written or read out is designated taking the addressing type of the peripheral equipment into consideration.
Accordingly, for example, an application program must be designed and programmed taking the addressing type of the peripheral equipment into consideration, which is cumbersome.